What is the difference between synchronous and asynchronous circuits?
What is the difference between synchronous and asynchronous circuits?
What is the difference between synchronous and asynchronous circuits? Answer: A synchronous circuit means that the clocks in the circuit are synchronized with each other. Synchronization is not limited to a single clock; it allows for multiple clocks, whose periods are multiples of each other and whose phase relationship is fixed. For example, a circuit with three clocks (10ns, 5ns, and 2.5ns) is a synchronous circuit. Our current synthesis and STA (Synchronization-Synchronization-Based Synchronization) are designed for synchronous circuits.
An asynchronous circuit refers to circuits whose periods are not multiples of each other or whose phase relationship is not fixed. For example, two clocks (5ns and 3ns) are asynchronous. Asynchronous circuits cannot be truly synthesized or STA-tested. If an asynchronous circuit is mixed within a synchronous circuit, `set_false_path` is used. Therefore, the correctness of asynchronous circuits can only be checked through simulation.
Asynchronous circuits are primarily combinational logic circuits used to generate read/write control signal pulses for address decoders, FIFOs, or RAM. However, they are also used in sequential circuits. In this case, they lack a unified clock, and the timing of state changes is unstable. Typically, the input signal only changes when the circuit is in a stable state. That is, only one input is allowed to change at a time to avoid race conditions between input signals. Circuit stability requires reliable setup and hold times, which will be discussed below.
Synchronous circuits are composed of sequential circuits (registers and various flip-flops) and combinational logic circuits. All their operations are performed under strict clock control. These sequential circuits share the same clock CLK, and all state changes occur on the rising (or falling) edge of the clock. For example, in a D flip-flop, when the rising edge arrives, the register transmits the level at the D terminal to the Q output.
The setup and hold time is discussed below. Setup time (tsu) refers to the time during which the data remains stable before the rising edge of the flip-flop's clock arrives. If the setup time is insufficient, data will not be latched into the flip-flop on the rising edge of the clock. The hold time (th) refers to the time after the rising edge of the flip-flop's clock that the data remains stable. If the hold time is insufficient, data will also not be latched into the flip-flop. Stable data transmission requires meeting both setup and hold time requirements; otherwise, the circuit will experience logic errors.
